        .nolist
#include <sys_config.h>
#include <hal/mips.h>
#include <hal/machine.h>
        .list

#define DEF_SP			0x9fc01ff0
#define DEF_RA			0xafc00000

#define MMFC0(rt,rd,sel)		\
	.word	0x40000000|(rt<<16)|(rd<<11)|sel

#define MMTC0(rt,rd,sel)		\
	.word	0x40800000|(rt<<16)|(rd<<11)|sel
	
#define InvAllScache			 0x03	     /* 0	3 */
#define IndexLoadTagScache		 0x07	     /* 1	3 */
#define IndexStoreTagScache		 0x0b	     /* 2	3 */
#define PageInvScache			 0x17	     /* 5	3 */
#define Index_Invalidate_I               0x0         /* 0       0 */
#define Index_Writeback_Inv_D            0x1         /* 0       1 */
#define Index_Load_Tag_I                 0x4         /* 1       0 */
#define Index_Load_Tag_D                 0x5         /* 1       1 */
#define Index_Store_Tag_I                0x8         /* 2       0 */
#define Index_Store_Tag_D                0x9         /* 2       1 */
#define Create_Dirty_Exc_D               0xD         /* 3       1 */
#define Hit_Invalidate_I                 0x10        /* 4       0 */
#define Hit_Invalidate_D                 0x11        /* 4       1 */
#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
#define Fill_I                           0x14        /* 5       0 */
#define Hit_Writeback_D                  0x19        /* 6       1 */
#define Hit_Writeback_I                  0x18        /* 6       0 */
#define COUNT_VAL 0x10000

	.text
	.set    noreorder
  .set    at
   
   .align  4     
	.globl  _start
	.ent    _start
_start:
	.set	mips32
# Step 1: Init CPU for boot up.
        mfc0    t0, C0_CONFIG
        li      t1, ~0x7
        and     t0, t1
        ori     t0, t0, 3
        mtc0    t0, C0_CONFIG            #cacheable, write-back
        mfc0	v0, C0_SR
				li		v1, 0x0002
				mtc0	v1, C0_SR			#Set up status register: Clear interrupt masks, Clear User mode, Clear ERL, Set EXL  
        mtc0    zero, $18			           #Disable watch exception
		    li      v1, 0x3
		    mtc0    v1, $19			             #Clear watch status bits
	 
		    mtc0	  zero, C0_CAUSE		       #Clear cause register
        
        lui     $14, 0x8000		# Get a KSeg0 address for cacheops

        # Clear TagLo/TagHi registers
        mtc0    $0, $28
        mtc0    $0, $29

        li      $15, 0x200	

        # Index Store Tag Cache Op
        # Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1:	
        .set mips3
        cache   0x8, 0($14)
        .set mips1
        addiu   $15, -1			# Decrement set counter

        bne     $15, $0, 1b
        addiu   $14, 0x20		# Get next line address

	
        lui     $14, 0x8000		# Get a KSeg0 address for cacheops

        # Clear TagLo/TagHi registers
        mtc0    $0,  $28
        mtc0    $0,  $29
        MMTC0(0,28,2)
        MMTC0(0,29,2)
        
        li      $15, 0x200		

        # Index Store Tag Cache Op
        # Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1:	
        .set mips3
        cache   0x9, 0($14)
        .set mips1
        addiu   $15, -1			# Decrement set counter

        bne     $15, $0, 1b
        addiu   $14, 0x20		# Get next line address
        la      t0,Test_RSA
        jr      t0
        nop
        .end _start
        
        .align  4   
        .globl  _clear_and_exit
        .ent    _clear_and_exit
_clear_and_exit:
         move  t0, sp
         subu  t1, t0, 0x1c00
1:       sw    zero, (t1)
         addiu t1, 4
         bltu  t1, t0, 1b
         nop  		     
         jr    ra
         nop            
        .set    at
        .set    reorder

